标题:A High-efficiency HEVC Entropy Decoding Hardware Architecture
作者:Sun, Hao; Zhou, Li; Xu, Hongji; Sun, Tao; Wang, Yang
通讯作者:Zhou, Li
作者机构:[Sun, Hao; Zhou, Li; Xu, Hongji; Wang, Yang] Shandong Univ, Sch Informat Sci & Engn, 27 South Shanda Rd, Jinan 250100, Peoples R China.; [Sun, Tao] 更多
会议名称:17th IEEE INTERNATIONAL CONFERENCE ON ADVANCED COMMUNICATIONS TECHNOLOGY (ICACT)
会议日期:JUL 01-03, 2015
来源:2015 17TH INTERNATIONAL CONFERENCE ON ADVANCED COMMUNICATION TECHNOLOGY (ICACT)
出版年:2015
卷:2015-August
页码:186-190
DOI:10.1109/ICACT.2015.7224781
关键词:HEVC; entropy; CABAC; architecture
摘要:High Efficiency Video Coding (HEVC) is becoming more and more important in current consumer application platforms. Compared with H.264 standard, it can reach up to 8192x4320 resolutions at 120fps. To accelerate HEVC decoding processing, this paper presents an efficient hardware entropy decoding architecture, Entropy decoding includes Colomb and CABAC decoding. Hierarchy ring buffer is designed to storage input bit-stream; Stack based Quad-Tree decoding structure is proposed for bit-stream parsing. Since CABAC decoder is a well-known bottleneck of the decoding performance, a 5-stage pipelined CABAC decoding engine is designed to accelerate the serial decoding progress. The proposed entropy decoding hardware architecture is verified on Altera Stratix IV FPGA running at a 200MHz clock frequency, using 8404 slices, memory size is 204KB.
收录类别:CPCI-S;EI;SCOPUS
资源类型:会议论文;期刊论文
原文链接:https://www.scopus.com/inward/record.uri?eid=2-s2.0-84949998418&doi=10.1109%2fICACT.2015.7224781&partnerID=40&md5=c584cccb0d9adf04d8b8a2e76078e49a
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