标题:Automatic data placement for CPU-FPGA heterogeneous multiprocessor System-on-Chips
作者:Li, Shiqing ;Wei, Yixun ;Ju, Lei
通讯作者:Ju, Lei
作者机构:[Li, Shiqing ;Wei, Yixun ;Ju, Lei ] School of Software, Shandong University, Jinan, China
会议名称:22nd Design, Automation and Test in Europe Conference and Exhibition, DATE 2019
会议日期:March 25, 2019 - March 29, 2019
来源:Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019
出版年:2019
页码:1379-1384
DOI:10.23919/DATE.2019.8715190
摘要:Efficient utilization of restrained memory resources is of paramount importance in CPU-FPGA heterogeneous multiprocessor system-on-chip (HMPSoC) based system design for memory-intensive applications. State-of-the-art high level synthesis (HLS) tools rely on the system programmers to manually determine the data placement within the complex memory hierarchy. In this paper, we propose an automatic data placement framework which can be seamlessly integrated with the commercial Vivado HLS. We first show counter-intuitive results that traditional frequency and locality based data placement strategy designed for CPU architecture leads to non-optimal system performance in CPU-FPGA HMPSoCs. Built on top of our memory latency analysis model, the proposed integer linear programming (ILP) based framework determines whether each array object should be access via the on-chip BRAM, shared CPU L2-cache, or DDR memory directly. Experimental results on the Zedboard platform show an average 1.39X performance speedup compared with a greedy-based allocation strategy.
© 2019 EDAA.
收录类别:EI
资源类型:会议论文
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