标题:A three-stage-write scheme with flip-bit for PCM main memory
作者:Li, Yanbin ;Li, Xin ;Ju, Lei ;Jia, Zhiping
通讯作者:Li, Xin
作者机构:[Li, Yanbin ;Li, Xin ;Ju, Lei ;Jia, Zhiping ] School of Computer Science and Technology, Shandong University, Jinan; 250101, China
会议名称:2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
会议日期:19 January 2015 through 22 January 2015
来源:20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
出版年:2015
页码:328-333
DOI:10.1109/ASPDAC.2015.7059026
摘要:Phase-change memory (PCM) is a nonvolatile memory which suffers slow write performance and limited write endurance. Besides, writing a one to a PCM cell needs longer time but less electrical current than writing a zero. In traditional PCM schemes, zeros and ones in a word are written at the same time and word write time has to be the time to write a one, thus incurring time waste. In this paper, we propose a three-stage write scheme with flip-bit for PCM main memory to reduce the number of changed bits and write latency. In our scheme, write operation is divided into comparison, write-0 and write-1 stages. In the comparison stage, new data and old data are compared and the new data is re-encoded by a flip-bit to minimize changed bits. Then the flip-bit and re-encoded data are written to PCM cells in an accelerating manner. All zero bits and one bits are written separately in later two stages to avoid the time waste in traditional write. Our scheme shrinks time consumption and reduces bit changes caused by write operation over other existing schemes. The experimental results show that this scheme decreases 43.5% bit changes, 16.6% write time and 34.6% write energy consumption on average. © 2015 IEEE.
收录类别:EI;SCOPUS
Scopus被引频次:8
资源类型:会议论文;期刊论文
原文链接:https://www.scopus.com/inward/record.uri?eid=2-s2.0-84926465991&doi=10.1109%2fASPDAC.2015.7059026&partnerID=40&md5=e289c1341a6121ab52a222cdbb6cdb69
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