标题:Managing hybrid on-chip scratchpad and cache memories for multi-tasking embedded systems
作者:Zhou, Zimeng ;Ju, Lei ;Jia, Zhiping ;Li, Xin
通讯作者:Ju, Lei
作者机构:[Zhou, Zimeng ;Ju, Lei ;Jia, Zhiping ;Li, Xin ] School of Computer Science and Technology, Shandong University, China
会议名称:2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
会议日期:19 January 2015 through 22 January 2015
来源:20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
出版年:2015
页码:423-428
DOI:10.1109/ASPDAC.2015.7059043
摘要:On-chip memory management is essential in design of high performance and energy-efficient embedded systems. While many off-the-shelf embedded processors employ a hybrid on-chip SRAM architecture including both scratchpad memories (SPMs) and caches, many existing work on SPM management ignore the synergy between caches and SPMs. In this work, we propose a static SPM allocation strategy for the hybrid on-chip memory architecture in a multi-tasking environment, which minimizes the overall access latency and energy consumption of the instruction memory subsystem. We capture cache conflict misses via a fine-grained temporal cache behavior model. An integer linear programming (ILP) based formulation is proposed to generate an function-level SPM allocation scheme, where both intra- and inter-task cache interference as well as access frequency are captured for an optimal memory subsystem design. Compared with the state-of-the-art static SPM allocation strategy in a multitasking environment, experimental results show that our SPM management scheme achieves 30.51% further improvement in instruction memory subsystem performance, and up to 34.92% in terms of energy saving. © 2015 IEEE.
收录类别:EI;SCOPUS
Scopus被引频次:3
资源类型:会议论文;期刊论文
原文链接:https://www.scopus.com/inward/record.uri?eid=2-s2.0-84926453104&doi=10.1109%2fASPDAC.2015.7059043&partnerID=40&md5=ed35507e7d97b6540750fa18eecedc05
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