标题:A 18.4M Triangles/s 122.6 mW Tile Co-processor for Embedded GPU Systems
作者:Wang, Jia; Sun, Tao; Zhou, Li; Zhang, Yuanzhi; Gao, Yuanyuan
通讯作者:Sun, T
作者机构:[Sun, Tao] Univ Jinan, Shandong Prov Key Lab Network Based Intelligent C, Jinan 250022, Peoples R China.; [Wang, Jia; Zhou, Li; Zhang, Yuanzhi; Gao, 更多
会议名称:International Conference on Mechatronics and Information Technology (ICMIT 2013)
会议日期:OCT 19-20, 2013
来源:PROGRESS IN MECHATRONICS AND INFORMATION TECHNOLOGY, PTS 1 AND 2
出版年:2014
卷:462-463
页码:1050-1054
DOI:10.4028/www.scientific.net/AMM.462-463.1050
关键词:tile-based render; GPU; triangle tiling; tile co-processor; architecture
摘要:This paper presents an efficient and accurate tile co-processor architecture which can be used in the tile based rendering systems. The design involves two key components, the vertex processing unit and the triangle tiling unit. The former part is used to get the vertices transformed, clipped and projected to generate the triangle list which located in the view frustum while the latter one reads in the triangle data and determines the tile list which indicates tiles that each triangle covers. A modified Bounding BOX (BBOX) test pipeline and a mask screening technology for different overlap types is proposed and employed in the design in order to get faster triangle binning with lower power consumption. The proposed architecture works at the frequency of 270 MHz, gains 18.4 M triangles tiling/sec with a power consumption less than 122.6 mW. The chip is implemented in 0.13 um CMOS technology and consumes 2.5 x 2.5 mm(2) totally.
收录类别:CPCI-S;EI;SCOPUS
资源类型:会议论文;期刊论文
原文链接:https://www.scopus.com/inward/record.uri?eid=2-s2.0-84891044567&doi=10.4028%2fwww.scientific.net%2fAMM.462-463.1050&partnerID=40&md5=c31c4cddc903dd0eab634efeafea7a97
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