标题:A parametric hardware fine acceleration/deceleration algorithm and its implementation
作者:Ji, Shuai; Hu, Tianliang; Zhang, Chengrui; Sun, Shuren
作者机构:[Ji, Shuai; Hu, Tianliang; Zhang, Chengrui; Sun, Shuren] Shandong Univ, Sch Mech Engn, Jinan 250061, Peoples R China.; [Ji, Shuai; Hu, Tianliang; Zh 更多
通讯作者:Hu, T
通讯作者地址:[Hu, TL]Shandong Univ, Sch Mech Engn, 17923 Jingshi Rd, Jinan 250061, Peoples R China.
来源:INTERNATIONAL JOURNAL OF ADVANCED MANUFACTURING TECHNOLOGY
出版年:2012
卷:63
期:9-12
页码:1109-1115
DOI:10.1007/s00170-012-3975-9
关键词:Motion control; Acceleration/deceleration; Interpolation; FPGA
摘要:Speed control is a very important factor to machining quality. In order to get high dynamic performance at the time of the machining speed changing, many kinds of algorithm for the acceleration/deceleration control have been proposed. The techniques which employ polynomial functions or digital convolution to generate velocity profile have been widely used and achieved good performance in motion control system. However, the control cycle of all these methods is one interpolation interval at least, and the velocity jump between two adjacent interpolation intervals during the acceleration/deceleration stage cannot be avoided. In this paper, a hardware fine acceleration/deceleration algorithm inside a single interpolation cycle is proposed to make the velocity change smoothly all the time even inside the interpolation interval. Based on this approach, an acceleration/deceleration fine interpolation circuit is designed with Verilog hardware description language and implemented in field programmable gate array. At last, the algorithm is applied in a three-axes motion controller and achieves a better machining performance than the one without this algorithm.
收录类别:EI;SCOPUS;SCIE
WOS核心被引频次:3
Scopus被引频次:5
资源类型:期刊论文
原文链接:https://www.scopus.com/inward/record.uri?eid=2-s2.0-84870053881&doi=10.1007%2fs00170-012-3975-9&partnerID=40&md5=b1490556433fffaa32a0698da19c02e2
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