标题:A full-mode FME VLSI architecture based on 8x8/4x4 adaptive Hadamard Transform for QFHD H.264/AVC encoder
作者:Liu, Jialiang ;Chen, Xinhua ;Fan, Yibo ;Zeng, Xiaoyang
通讯作者:Liu, J.
作者机构:[Liu, Jialiang ;Chen, Xinhua ] College of Information Science and Engineering, Shandong University of Science and Technology, Qingdao, China;[Fan, Yib 更多
会议名称:2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011
会议日期:October 3, 2011 - October 5, 2011
来源:2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011
出版年:2011
页码:434-439
DOI:10.1109/VLSISoC.2011.6081622
摘要:Adaptive Block-size Transform (ABT) has been added to H.264/AVC standard with the Fidelity Range Extension. In this paper, we apply this ABT concept to our FME design and propose a full-mode FME architecture based on 8x8/4x4 adaptive Hadamard Transform. This technique can avoid unifying all variable block-size blocks into 4x4-size blocks and improve the encoding performance. We also exploit the linearity of Hadamard Transform in quarter-pel refinement and decrease the cycles caused by the second long search process. In architecture level, we employ two interpolating engines that can support 8-pel and 4-pel input to time-share one SATD (Sum of Absolute Hadamard Transform) Generator. These strategies can increase parallelism and reduce the cycles efficiently. Besides, this design can support full modes, which guarantees the encoding performance. Experimental results show that our design can achieve real-time processing for QFHD@30fps at the operation frequency of 320MHz with 444.6K gates hardware. © 2011 IEEE.
收录类别:EI
资源类型:会议论文
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