标题:Shared write buffer to support speculative execution
作者:Ye, John ;Dai, Hongjun ;Li, Songyuan ;Chen, Tianzhou
作者机构:[Ye, John ;Li, Songyuan ;Chen, Tianzhou ] College of Computer Science, Zhejiang University, Hangzhou, China;[Dai, Hongjun ] College of Computer Scienc 更多
会议名称:17th IEEE International Conference on High Performance Computing and Communications, IEEE 7th International Symposium on Cyberspace Safety and Security and IEEE 12th International Conference on Embedded Software and Systems, HPCC-ICESS-CSS 2015
会议日期:24 August 2015 through 26 August 2015
来源:Proceedings - 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security and 2015 IEEE 12th International Conference on Embedded Software and Systems, HPCC-CSS-ICESS 2015
出版年:2015
页码:1494-1499
DOI:10.1109/HPCC-CSS-ICESS.2015.310
关键词:Cache; Multi-Core; Shared Write Buffer; Speculative Multi-Threading
摘要:With the trend of growing number of integrated processing cores on Chip Multiprocessors (CMPs), researchers are working hard to increase the available parallelism of software programs so as to efficiently harness the growing computing power. One noticeable direction among these efforts is Speculative Multi-threading (SpMT), a.k.a Thread Level Speculation (TLS), which aims to extract Thread Level Parallelism (TLP) by split a sequential execution thread into several finer ones and execute them on parallel. A SpMT thread is in speculative status before it 'knows' all its input data are correct. A speculative thread needs to write to the L1 cache, but its output might be discarded if the speculation eventually fails. However, another speculative thread may have already read in such speculative output. Some mechanism is in need to support speculative read and write. And because the SpMT threads are extracted from a single thread, they usually share lots of data, thus there might be intense data coherence among the L1 caches. It would be very complicated to support data coherence and speculation together. Therefore we propose a Shared Write Buffer among the SpMT cores. With SWB, we could confine the speculative read and write in the SWB, thus the speculation will not interference with coherence, and the L1 cache design could be drastically simplified. Experiments show that the SWB can capture a big portion of inter-core data sharing, reduce cache coherence, and drastically improve data access performance. © 2015 IEEE.
收录类别:EI;SCOPUS
资源类型:会议论文;期刊论文
原文链接:https://www.scopus.com/inward/record.uri?eid=2-s2.0-84961707822&doi=10.1109%2fHPCC-CSS-ICESS.2015.310&partnerID=40&md5=2142255f606b81a3a72b3ba654f04afc
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