标题:NVM-Based FPGA Block RAM With Adaptive SLC-MLC Conversion
作者:Ju, Lei; Sui, Xiaojin; Li, Shiqing; Zhao, Mengying; Xue, Chun Jason; Hu, Jingtong; Jia, Zhiping
通讯作者:Zhao, MY;Zhao, Mengying
作者机构:[Ju, Lei; Sui, Xiaojin; Li, Shiqing] Shandong Univ, Sch Software, Jinan 250101, Shandong, Peoples R China.; [Zhao, Mengying; Jia, Zhiping] Shandong 更多
会议名称:Embedded Syst Week (ESWEEK) / Int Conf on Compilers, Architecture, and Synthesis for Embedded Syst (CASES) / Int Conf on Hardware/Software Codesign and Syst Synthesis (CODES+ISSS) / ACM SIGBED Int Conf on Embedded Software (EMSOFT)
会议日期:MAR 27-APR 03, 2018
来源:IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
出版年:2018
卷:37
期:11
页码:2661-2672
DOI:10.1109/TCAD.2018.2857261
关键词:Block RAM (BRAM); design flow; field-programmable gate array (FPGA);; multilevel cell (MLC); nonvolatile memory (NVM)
摘要:The capacity of SRAM-based FPGA block RAM (BRAM) is restrained by the low density and high leakage power of the current CMOS technology. In this paper, we propose a nonvolatile memory (NVM)-based BRAM architecture which enables flexible conversions between single-level cell (SLC) and multilevel cell (MLC) states. We show that despite the high per-access latency and power consumption, MLC-based BRAM blocks reduce the routing cost between logic units and on-chip data storages, which potentially leads to a smaller critical path delay and power consumption. Therefore, we propose an NVM BRAM architecture and an EDA framework which adaptively packs data into SLC- or MLC-state BRAMs during FPGA design flow in order to achieve better system performance. This paper illustrates that a simple memory device replacement from SRAM to NVM leads to nonoptimal system performance. On the other hand, compared with operating all NVM BRAM blocks in the SLC state with better per-access latency and power consumption, the proposed hybrid SLC- MLC architecture and design flow improves the critical path delay by 18.51%, with a system power reduction of 25.83% at the same time. Moreover, compared with the traditional "fast" SRAM-based BRAM blocks under the same BRAM area constraint, our hybrid NVM BRAM architecture improves the critical path delay by 8.55% on average, with an average system power reduction of 54.34% at the same time.
收录类别:CPCI-S;EI;SCOPUS;SCIE
资源类型:会议论文;期刊论文
原文链接:https://www.scopus.com/inward/record.uri?eid=2-s2.0-85050214428&doi=10.1109%2fTCAD.2018.2857261&partnerID=40&md5=49e8762be7dd91bc1e4531ef06b78788
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